1. Field of the Invention
The present invention relates to a pattern and method for measuring an alignment error in the lithography process employed in the manufacture of a semiconductor device.
2. Description of the Related Art
As the integration degree of a semiconductor device increases, the minimum design rule decreases, and the resolution of the lithography technique increases accordingly. Along with an increase in resolution, the alignment precision between a pattern preformed on a wafer and a projection image projected through an exposure mask used in the lithography process also increases. High precision is therefore required in measurement of an alignment error.
Regarding a method of measuring an alignment error, a method of comparing a lower pattern for alignment error measurement and an upper pattern with an optical microscope, a method of forming an opening as an upper pattern in an insulating film, and observing a lower pattern under the insulating film through the opening, thereby comparing the lower and upper patterns, and the like are conventionally proposed.
With the method of comparing the lower pattern for alignment error measurement and the upper pattern with the optical microscope, sufficiently high precision cannot be obtained due to the limitation in resolution of the optical microscope. An alignment error in a semiconductor device of the half micron or submicron generation cannot therefore be measured at high precision.
A scanning electron microscope has a higher resolution than that of an optical microscope and is used in the lithography process to measure the width of patterned line or the diameter of opening. However, the scanning electron microscope allows to observe an image formed by secondary electrons generated from the surface of an observation target. When the lower pattern is covered with an interlayer insulating film or the like, this lower pattern cannot be observed. Therefore, it is difficult to measure an alignment error by using the scanning electron microscope.
With the method of forming an opening as an upper pattern in the insulating film and observing the lower pattern under the insulating film through the opening, thereby comparing the lower and upper patterns, when an interlayer insulating film or the like is formed on the opening, it is also difficult to measure an alignment error by using a scanning electron microscope.
With any conventional methods, an alignment error cannot be electrically measured. Therefore, an alignment error in a semiconductor device cannot be easily measured after the manufacture.